Method of fabricating an integrated circuit through utilizing metal layers to program randomly positioned basic units

ABSTRACT

A method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The method includes forming a plurality of basic units with the same component characteristic on the semiconductor body, and forming at least a layout layer to program the basic units for building a clocked logic circuit and a non-clocked logic circuit without placing restrictions on positions of the clocked logic circuit and the non-clocked logic circuit on the semiconductor body.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a metalprogrammable integrated circuit, and more specifically, to a method offabricating an integrated circuit through utilizing metal layers toprogram randomly positioned basic units.

2. Description of the Prior Art

FIG. 1 is a diagram showing a prior art semiconductor body 10 of anintegrated circuit. The semiconductor body has a plurality of functionalcircuit cells 12. The functional circuit cells 12 are arrangedrow-by-row or column-by-column according to an array format to finallyform a matrix format. It is well-known that the matrix formatcorresponds to a minimum chip size. That is, the allocation of thefunctional circuit cells 12 corresponds to a maximum component density.

The semiconductor body 10 is divided into synchronous regions 14 a, 14 band a non-synchronous region 16. All of the functional circuit cells 18a, 18 b within the synchronous regions 14 a, 14 b operate according to aclock signal. For example, each of the functional circuit cells 18 a, 18b respectively functions as a flip-flop, a latch, or a clock bufferafter being defined by a corresponding routing design. On the otherhand, the functional circuit cells 20 within the non-synchronous region16 are not driven by clock signals.

Each functional circuit cell 20 is capable of performing a predeterminedlogic operation after being defined by a corresponding routing design.For example, each of the functional circuit cells 20 respectivelyfunctions as an AND logic gate circuit, an OR logic gate circuit, or anXOR logic gate circuit. After the integrated circuit designer hands overthe designed photomask patterns to the maker of the semiconductor body10, upper metal layers are then formed on the semiconductor body 10based on the photomask patterns.

Please refer to FIG. 1 in conjunction with FIG. 2. FIG. 2 is a diagramshowing traces routed within the synchronous regions 14 a, 14 b. In thesynchronous region 14 a, a clock trace 22 a vertically crosses eachfunctional circuit cell 18 a of the synchronous region 14 a. Inaddition, two power traces 24 a, 26 a also cross each functional circuitcell 18 a of the synchronous region 14 a. The power traces 24 a, 26 aare respectively used to provide operating voltages (a high voltagelevel Vdd and a low voltage level Vss for example) required by eachfunctional circuit cell 18 a. Similarly, a clock trace 22 b and twopower traces 24 b, 26 b vertically cross each functional circuit cell 18b of the synchronous region 14 b. As shown in FIG. 2, power traces 24 a,24 b, 26 a, 26 b are respectively located at both sides of the clocktraces 22 a, 22 b so that noise transmitted by the clock traces 22 a, 22b interfering with the clock signals is reduced. In other words, clockskew related to the clock signal is lessened.

As mentioned above, the semiconductor body 10 of the prior artintegrated circuit is divided into synchronous regions 14 a, 14 b and anon-synchronous region 16. The functional circuit cells 18 a, 18 b,driven by the clock signals, are distributed in the synchronous regions14 a, 14 b. That is, the prior art has to consider clock balance forcontrolling clock skew according to the geometric distribution of thesynchronous regions 14 a, 14 b within the semiconductor body 10.However, based on the prior art, the semiconductor body 10 is requiredto define the synchronous regions 14 a, 14 b and the non-synchronousregion 16. Therefore, when programming the semiconductor body 10 toperform a predetermined logic operation, the IC designer needs toconsider the allocation of the synchronous regions 14 a, 14 b and thenon-synchronous region 16 on the semiconductor body 10. It is obviousthat the allocation of the synchronous regions 14 a, 14 b and thenon-synchronous region 16 on the prior art semi-conductor body 10 isfixed. Therefore, it is impossible to elastically program traces routedamong the transistors within the synchronous regions 14 a, 14 b and thenon-synchronous region 16 for implementing another predetermined logicoperation mentioned above.

Because the synchronous regions 14 a, 14 b and the non-synchronousregion 16 on the semiconductor body 10 are defined according to apredetermined ratio, say, the ratio of transistors within thesynchronous regions 14 a, 14 b to the transistors within thenon-synchronous region 16, for respectively establishing the clockedlogic circuits and the non-clocked logic circuits, the application fieldof the semiconductor body 10 is limited by the fixed allocation of thesynchronous regions 14 a, 14 b and the non-synchronous region 16. Thatis, the application elasticity of the prior art semiconductor body 10 isbad.

SUMMARY OF INVENTION

It is therefore a primary objective of the claimed invention to providea method of programming basic units randomly positioned on asemiconductor body for forming either a clocked logic circuit or anon-clocked logic circuit according to different requirements.

Briefly summarized, a preferred embodiment discloses a method offabricating an integrated circuit. The integrated circuit has asemiconductor body. The claimed method includes forming a plurality ofbasic units on the semiconductor body, each of the basic units having anidentical device characteristic, and forming at least a layout layer toprogram the basic units for generating a clocked logic circuit and anon-clocked logic circuit without placing restrictions on positions ofthe clocked logic circuit and the non-clocked logic circuit on thesemiconductor body.

According to the preferred embodiment, another claimed method offabricating the integrated circuit includes forming a plurality of basicunits on the semiconductor body, each of the basic units having aplurality of first transistors cascaded in a series and a plurality ofsecond transistors cascaded in a series, and forming at least a layoutlayer to program traces among the first transistors and the secondtransistors of at least a basic unit for controlling the basic unit toform either a clocked logic circuit or a non-clocked logic circuit.

The preferred embodiment discloses an integrated circuit, and theclaimed integrated circuit includes a semiconductor body for positioninga plurality of basic unit, each of the basic units having an identicaldevice characteristic; a clocked logic circuit formed on thesemiconductor body, the clocked logic circuit being formed by at least abasic unit; and a non-clocked logic circuit formed on the semiconductorbody, the non-clocked logic circuit being formed by at least a basicunit. The semiconductor body does not limit locations of the clockedlogic circuit and the non-clocked logic circuit formed on thesemiconductor body.

According to the preferred embodiment, another claimed integratedcircuit includes a semiconductor body for positioning a plurality ofbasic units, each of the basic units having a plurality of firsttransistors cascaded in a series and a plurality of second transistorscascaded in a series, a clocked logic circuit formed on thesemiconductor body, and a non-clocked logic circuit formed on thesemiconductor. The clocked logic circuit is formed by at least a basicunit, and the non-clocked logic circuit is formed by at least a basicunit.

The claimed method forms a plurality of basic units on a semiconductorbody, wherein the allocation of basic units on the semiconductor body isnot divided into a synchronous region and a non-synchronous region.Then, the method according to the present invention dynamicallydetermines how many basic units are required to form clocked logiccircuits and how many basic units are needed to form non-clocked logiccircuits according to functionality of different integrated circuits.Therefore, the same semiconductor bodies are easily programmed by metallayers to produce different integrated circuits.

These and other objectives of the claimed invention will no doubt becomeobvious to those of ordinary skill in the art at reading the followingdetailed description of the preferred embodiments that are illustratedin the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing a prior art semiconductor body of anintegrated circuit.

FIG. 2 is a diagram showing traces routed within the synchronousregions.

FIG. 3 is a diagram showing a semiconductor body according to thepresent invention.

FIG. 4 is a diagram of a basic unit shown in FIG. 3.

FIG. 5 is a diagram illustrating inverters established by the basic unitaccording to the present invention.

FIG. 6 is an equivalent circuit diagram of the inverters shown in FIG.5.

FIG. 7 is a diagram illustrating an NOR gate established by the basicunit according to the present invention.

FIG. 8 is an equivalent circuit diagram of the NOR gate shown in FIG. 7.

FIG. 9 is a diagram illustrating a flip-flop established by basic unitsaccording to the present invention.

FIG. 10 is an equivalent circuit diagram of the flip-flop shown in FIG.9.

FIG. 11 is a diagram of another basic unit according to the presentinvention.

FIG. 12 is a diagram illustrating a multiplexer established by the basicunit shown in FIG. 11.

FIG. 13 is an equivalent circuit diagram of the multiplexer shown inFIG. 12.

DETAILED DESCRIPTION

Please refer to FIG. 3, which is a diagram showing a semiconductor body40 according to the present invention.

The semiconductor body 40 has a plurality of basic units 42. In thepreferred embodiment, the basic units 42 are positioned on thesemiconductor body 40 according to a matrix format for acquiring greaterdensity. In other words, the area required to accommodate the basicunits 42 is reduced to further shrink size of the correspondingintegrated circuit. It is well-known that a semiconductor foundryfabricates the semiconductor body 40 in advance. An integrated circuitdesigner is then capable of designing photomask patterns for tracesrouted among the basic units 42. In the end, according to the photomaskpatterns designed by the integrated circuit designer, the semiconductorfoundry forms at least a metal layer upon the semiconductor body 40 toposition conductive wires routed among the basic units 42. Therefore, asingle basic unit 42 or a group of basic units 42 can be programmed tomake the integrated circuit capable of performing a predetermined logicoperation according to the design defined by the IC designer.

Please refer to FIG. 4, which is a diagram of the basic unit 42 shown inFIG. 3. In the preferred embodiment, six transistors 44 a, 44 b, 44 c,46 a, 46 b, 46 c are positioned within the basic unit 42, whereintransistors 44 a, 44 b, 44 c are PMOS transistors, and transistors 46 a,46 b, 46 c are NMOS transistors. In addition, transistors 44 a, 44 b, 44c are cascaded in a series, and transistors 46 a, 46 b, 46 b arecascaded in a series as well. As shown in FIG. 3, a plurality of basicunits 42 are allocated on the semiconductor body 40. It is obvious fromFIG. 4 that one basic unit 42 only contains transistors 44 a, 44 b, 44c, 46 a, 46 b, 46 c. The allocation of basic units 42 is not dividedinto a synchronous region and a non-synchronous region as the prior artdoes. In other words, the randomly positioned basic units 42 accordingto the present invention are programmed to establish either a clockedlogic circuit or a non-clocked logic circuit through metal layers.Therefore, when the basic units 42 are programmed, they are not dividedinto two groups (a synchronous region and a non-synchronous region forexample) according to their locations. That is, no restriction is placedon positions of the clocked logic circuit and the non-clocked logiccircuit on the semiconductor body when the basic units 42 are programmedto form the clocked logic circuit and the non-clocked logic circuit.Concerning the clocked logic circuit, it can be a flip-flop or a latch.With regard to the non-clocked logic circuit, it can function as aspecific logic gate or a look-up table.

In the preferred embodiment, gates, sources, and drains of thetransistors 44 a, 44 b, 44 c correspond to a plurality of programmingnodes N₁, N₂, N₃, N₄, N₅, N₆, N₇. In addition, gates, sources, anddrains of the transistors 46 a, 46 b, 46 c also correspond to aplurality of programming nodes N₈, N₉, N₁₀, N₁₁, N₁₂, N₁₃, N₁₄.Therefore, the logic operation run by the basic unit 42 is programmedand defined through the programming nodes N₁-N₁₄. Please refer to FIG. 5in conjunction with FIG. 6. FIG. 5 is a diagram illustrating inverters48 a, 48 b established by the basic unit 42 according to the presentinvention, and FIG. 6 is an equivalent circuit diagram of the inverters48 a, 48 b shown in FIG. 5.

For the inverters 48 a, 48 b shown in FIG. 5, the programming node N₁ iselectrically connected to the programming node N_(8,) the programmingnode N₂ is electrically connected to the programming node N9, theprogramming node N₄ is electrically connected to the programming nodeN_(11,) the programming node N₅ is electrically connected to theprogramming node N_(12,) the programming node N₃ is electricallyconnected to a high voltage level (V_(dd) for example), and theprogramming node N₁₀ is electrically connected to a low voltage level(GND for example) through routing traces provided by at least a metallayer. In addition, programming nodes N₁, N₈ correspond to an outputport OUT₁, programming nodes N₂, N₉ correspond to an input port IN₁,programming nodes N₄, N₁₁ correspond to an input port IN₂, andprogramming nodes N₅, N₁₂ correspond to an output port OUT₂.

Concerning the inverter 48 a, the transistor 46 a within the inverter 48a is turned on, and the transistor 44 a is turned off when the inputport IN₁ is driven by a high voltage level (V_(dd) for example). Inother words, the voltage level of the output port OUT₁ approaches a lowvoltage level (GND for example). On the contrary, the transistor 44 awithin the inverter 48 a is turned on, and the transistor 46 a is turnedoff when the input port IN₁ is driven by a low voltage level (GND forexample). That is, the voltage level of the output port OUT₁ approachesa high voltage level (V_(dd) for example). Therefore, an equivalentcircuit representing the inverter 48 a is shown in FIG. 6.

For the inverter 48 b, it has functionality identical to that of theinverter 48 a. When the input port IN₂ is driven by a high voltage level(V_(dd) for example), the transistor 46 b within the inverter 48 b isturned on, and the transistor 44 b remains off. In other words, thevoltage level of the output port OUT₂ approaches a low voltage level(GND for example). On the contrary, the transistor 44 b within theinverter 48 b is turned on, and the transistor 46 b remains off when theinput port IN₂ is driven by a low voltage level (GND for example).Therefore, the voltage level of the output port OUT₂ approaches a highvoltage level (V_(dd) for example). Similarly, an equivalent circuitrepresenting the inverter 48 a is shown in FIG. 6. From the abovedescription, the basic units 42 according to the present invention arecapable of establishing any non-clocked logic circuits on thesemiconductor body 42 with the help of the routing traces programmed bymetal layers.

Please refer to FIG. 7 in conjunction with FIG. 8. FIG. 7 is a diagramillustrating an NOR gate 50 established by the basic unit 42 accordingto the present invention, and FIG. 8 is an equivalent circuit diagram ofthe NOR gate 50 shown in FIG. 7. For programming the basic unit 42 toestablish the NOR gate 50 shown in FIG. 7, at least a metal layer isutilized to implement required routing traces. Consequently, theprogramming node N₁ is electrically connected to a high voltage level(V_(dd) for example), the programming node N₈ is electrically connectedto a low voltage level (GND for example), the programming node N₂ iselectrically connected to the programming node N₉, the programming nodeN₄ is electrically connected to the programming node N₁₁, theprogramming node N₆ is electrically connected to the programming nodeN₁₃, and the programming node N₇ is electrically connected to theprogramming nodes N₁₀, N₁₄. In addition, programming nodes N₂, N₉correspond to an input port IN₁, programming nodes N₄, N₁₁ correspond toan input port IN₂, programming nodes N₆, N₁₃ correspond to an input portIN₃, and programming nodes N₇, N₁₀, N₁₄ correspond to an output portOUT.

Because all of the transistors 46 a, 46 b, 46 c are NMOS transistors,the output port OUT is forced to correspond to the low voltage level(GND for example) when one of the input ports IN₁, IN₂, IN₃ is driven bythe high voltage level to turn on a corresponding transistor 46 a, 46 b,46 c. However, the transistors 44 a, 44 b, 44 c are PMOS transistors andcascaded in a series. Therefore, the output port OUT is allowed to havea voltage level equaling the high voltage level (V_(dd) for example)only when all of the input ports IN₁, IN₂, IN₃ are driven by the lowvoltage level (GND for example). At this time, all of the transistors 44a, 44 b, 44 c are turned on, and the transistors 46 a, 46 b, 46 c areswitched off. An equivalent circuit standing for the NOR gate 50 isshown in FIG. 8. It is clear from the above description that the basicunits 42 according to the present invention are capable of establishingany non-clocked logic circuits on the semiconductor body 42 with thehelp of the routing traces programmed by metal layers.

In the preferred embodiment, the basic unit 42 has 6 transistors 44 a,44 b, 44 c, 46 a, 46 b, 46 c. As mentioned above, one basic unit 42 andappropriate routing traces are capable of building a circuit structurecorresponding to the inverter 48 a, 48 b or the NOR gate 50. However, itis impossible to utilize just one basic unit and appropriate routingtraces to establish all kinds of logic circuits. Therefore, the methodaccording to the present invention makes use of a plurality of basicunits and appropriate routing traces to build a complicated logiccircuit such as a flip-flop.

Please refer to FIG. 9 in conjunction with FIG. 10. FIG. 9 is a diagramillustrating a flip-flop 60 established by basic units 42 a, 42 b, 42 caccording to the present invention, and FIG. 10 is an equivalent circuitdiagram of the flip-flop 60 shown in FIG. 9. Concerning the basic unit42 a shown in FIG. 9, the programming node N₁ is electrically connectedto a high voltage level (V_(dd) for example), the programming node N₈ iselectrically connected to a low voltage level (GND for example), theprogramming node N₂ is electrically connected to the programming nodeN₉, the programming node N₄ is electrically connected to the programmingnode N₁₃, the programming node N₆ is electrically connected to theprogramming node N₁₁, and the programming node N₇ is electricallyconnected to the programming node N₁₄ with the help of the traces routedon at least a metal layer.

With regard to another basic unit 42 b, the programming node N₁ iselectrically connected to the programming node N₈, the programming nodeN₂ is electrically connected to the programming node N₉, the programmingnode N₃ is electrically connected to a high voltage level (V_(dd) forexample), the programming node N₁₀ is electrically connected to a lowvoltage level (GND for example), the programming node N₄ is electricallyconnected to the programming node N₁₁, and the programming node N₅ iselectrically connected to the programming node N₁₂ with the help of thetraces routed on at least a metal layer.

Concerning the last basic unit 42 c, the programming node N₁ iselectrically connected to a high voltage level (V_(dd) for example), theprogramming node N₈ is electrically connected to a low voltage level(GND for example), the programming node N₂ is electrically connected tothe programming node N₉, the programming node N₄ is electricallyconnected to the programming node N₁₃, the programming node N₆ iselectrically connected to the programming node N₁₁, and the programmingnode N₇ is electrically connected to the programming node N₁₄ with thehelp of the traces routed on at least a metal layer. In addition, basicunits 42 a, 42 b, 42 c are electrically connected through proper routingtraces. That is, programming nodes N₂, N₉ of the basic unit 42 a areelectrically connected to programming nodes N₁, N₈ of the basic unit 42b and programming nodes N₇, N₁₄ of the basic unit 42 c, programmingnodes N₅, N₁₂ of the basic unit 42 a are electrically connected toprogramming nodes N₂, N₉ of the basic unit 42 b, programming nodes N₄,N₁₁ of the basic unit 42 b are electrically connected to programmingnodes N₅, N₁₂ of the basic unit 42 c, and programming nodes N₅, N₁₂ ofthe basic unit 42 b are electrically connected to programming nodes N₂,N₉ of the basic unit 42 c.

In addition, a clock signal CLK is respectively inputted into theprogramming node N₆ of the basic unit 42 a and the programming node N₁₃of the basic unit 42 c, and another clock signal

-   -   {overscore (CLK)}        , which is an inverted signal of the clock signal CLK, is        inputted into the programming node N₁₃ of the basic unit 42 a        and the programming node N₆ of the basic unit 42 c. The clock        signal CLK and the clock signal    -   {overscore (CLK)}        are used for controlling transistor switches formed by the NMOS        transistors and PMOS transistors.

As shown in FIG. 9, the basic units 42 a, 42 c have similar routingdesigns. That is, the basic unit 42 a is used to establish the circuitunit 62 shown in FIG. 10, and the basic unit 42 c is used to establishthe circuit unit 64 shown in FIG. 10. For the basic unit 42 a, theprogramming nodes N₇, N₁₄ function as an input port IN of the flip-flop60. With regard to the basic unit 42 c, the programming nodes N₂, N₄function as an output port OUT of the flip-flop 60. Taking the circuitstructure corresponding to the basic unit 42 a for example, it isobvious from the circuit structures of the inverters 48 a, 48 b shown inFIG. 5 that the transistors 44 a, 46 a are used to establish an inverter65.

In addition, the gate (the programming node N₁₃) of the transistor 46 cis connected to the gate (the programming node N₄) of the transistor 44b, and the gate (the programming node N₆) of the transistor 44 c isconnected to the gate (the programming node N₁₁) of the transistor 46 b.The voltage level of the clock signal CLK, therefore, is used to turn onone of the transistor switch 66 formed by transistors 44 c, 46 c and thetransistor switch 67 formed by the transistors 44 b, 46 b. That is, whenthe transistor switch 66 is turned on, the transistor switch 67 isturned off accordingly. On the other hand, when the transistor switch 67is turned on, the transistor switch 66 is turned off accordingly.Similarly, it is known that basic unit 42 b within the flip-flop 60 isused to establish the inverter 68 corresponding to the circuit unit 62and the inverter 69 corresponding to the circuit unit 64 according tothe circuit structures of the inverters 48 a, 48 b shown in FIG. 5. Asmentioned above, the basic units 42 according to the present invention,therefore, are capable of establishing any clocked logic circuits on thesemiconductor body 42 with the help of the routing traces programmed bymetal layers.

Please note that the basic unit 42 as shown in FIG. 4 only has 6transistors 44 a, 44 b, 44 c, 46 a, 46 b, 46 c. However, the basic unit42 according to the present invention is not limited to a fixed amountof transistors. That is, the basic unit 42 is allowed to include aplurality of transistors. Therefore, a single basic unit 42 or a groupof basic units 42 can be programmed to perform a predetermined logicoperation through metal layers. Please refer to FIGS. 11, 12, and 13.FIG. 11 is a diagram of another basic unit 70 according to the presentinvention. FIG. 12 is a diagram illustrating a multiplexer 76established by the basic unit 70 shown in FIG. 11. FIG. 13 is anequivalent circuit diagram of the multiplexer 76 shown in FIG. 12. Thebasic unit 70 has 8 transistors 72 a, 72 b, 72 c, 72 d, 74 a, 74 b, 74c, 74 d, wherein transistors 72 a, 72 b, 72 c, 72 d are PMOStransistors, and transistors 74 a, 74 b, 74 c, 74 d are NMOStransistors. In addition, transistors 72 a, 72 b, 72 c, 72 d arecascaded in a series, and transistors 74 a, 74 b, 74 c, 74 d arecascaded in a series as well. As shown in FIG. 3, the basic units 70 andthe basic units 42 are positioned according to the same rule mentionedbefore. In other words, the allocation of the basic units 70 is notdivided into a synchronous region and a non-synchronous region, and thebasic units 70 are programmed to establish either a clocked logiccircuit or a non-clocked logic circuit with the help of the metallayers. Similarly, gates, sources, and drains of the transistors 72 a,72 b, 72 c, 72 d, 74 a, 74 b, 74 c, 74 d correspond to a plurality ofprogramming nodes N₁-N₁₈. Therefore, the traces routed among theprogramming nodes N₁-N₈ are controlled to achieve the objective ofprogramming functionality of the basic unit 70.

Concerning the basic unit 70 shown in FIG. 12, the programming nodes N₁,N₉ are electrically connected to a high voltage level (V_(dd) forexample), programming nodes N₁₀, N₁₈ are electrically connected to a lowvoltage level (GND for example), the programming node N₂ is electricallyconnected to the programming node N₁₁, the programming node N₃ iselectrically connected to the programming node N₁₂, the programming nodeN₄ is electrically connected to the programming node N_(15,) theprogramming node N₆ is electrically connected to the programming nodeN₁₃, the programming node N₇ is electrically connected to theprogramming node N₁₆, and the programming node N₈ is electricallyconnected to the programming node N₁₇. In addition, a selecting signalSEL is inputted into the programming node N₁₅, and another selectingsignal

-   -   {overscore (SEL)}        , which is an inverted signal of the selecting signal SEL, is        inputted to the programming node N₆. In the preferred        embodiment, programming nodes N₂, N₁₁ function as an input port        IN₁, programming nodes function as another input port IN₂, and        programming nodes N₅, N₁₄ function as an output port OUT.

Transistors 72 a, 74 a are used to form the inverter 77 a shown in FIG.13, and the programming nodes N₃, N₁₂ correspond to an output port ofthe inverter 77 a. Similarly, transistors 72 d, 74 d are used to formanother inverter 77 b shown in FIG. 13, and the programming nodes N₇,N₁₆ correspond to an output port of the inverter 77 b. In addition,transistors 72 b, 74 b are used to establish the transistor switch 78 ashown in FIG. 13, and transistors 72 c, 74 c are used to establishanother transistor switch 78 b shown in FIG. 13. Please note that thegate (the programming node N₁₅) of the transistor 74 c is connected tothe gate (the programming node N₄) of the transistor 72 b, and the gate(the programming node N₆) of the transistor 72 c is connected to thegate (the programming node N₁₃) of the transistor 74 b. The selectingsignal SEL, therefore, is capable of turning on one of the transistorswitches 78 a, 78 b. That is, when the transistor switch 78 a is turnedon, the peer transistor switch 78 b is turned off accordingly.Therefore, a signal inputted into the input port IN₁ is successfullyoutputted from the output port OUT. On the other hand, when thetransistor switch 78 b is turned on, the peer transistor switch 78 a isturned off accordingly. Therefore, a signal inputted into the input portIN₂ is successfully outputted from the output port OUT. In other words,the multiplexer 76 functions as a 2:1 multiplexer.

The basic unit 70 includes 8 transistors, and it still can be programmedto establish a non-clocked logic circuit on the semiconductor body 40through the traces routed on the metal layers. For the circuit structureshown in FIG. 9, it is easily implemented with 3 basic units 70.Therefore, the basic units 70 can be programmed to establish a clockedlogic circuit on the semiconductor body 40 as well through the tracesrouted on the metal layers. To sum up, the present invention does notlimit the number of transistors within a basic unit to a fixed value.That is, either a single basic unit or a group of basic units can beused to establish any clocked logic circuits or non-clocked logiccircuits with the help of traces properly routed on the metal layers.

In contrast to the prior art, the method of fabricating an integratedcircuit according to the present invention forms a plurality of basicunits on a semiconductor body, wherein the allocation of basic units onthe semiconductor body is not divided into a synchronous region and anon-synchronous region. Then, the method according to the presentinvention dynamically determines how many basic units are required toform clocked logic circuits and how many basic units are needed to formnon-clocked logic circuits according to functionality of differentintegrated circuits. In other words, the method according to the presentinvention is capable of adjusting an amount of basic units correspondingto the clocked region and an amount of transistors corresponding to thenon-clocked region. Therefore, the same semiconductor bodies are easilyprogrammed by metal layers to produce different integrated circuits.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device may be made while retainingthe teachings of the invention. Accordingly, the above disclosure shouldbe construed as limited only by the metes and bounds of the appendedclaims.

1. A method of fabricating an integrated circuit, the integrated circuithaving a semiconductor body, the method comprising following steps:(a)forming a plurality of basic units on the semiconductor body, each ofthe basic units having an identical device characteristic; and(b)forming at least a layout layer to program the basic units forgenerating a clocked logic circuit and a non-clocked logic circuitwithout placing restrictions on positions of the clocked logic circuitand the non-clocked logic circuit on the semiconductor body.
 2. Themethod of claim 1 wherein step (a) forms at least a transistor withineach of the basic units.
 3. The method of claim 2 wherein the transistoris an MOS transistor.
 4. The method of claim 1 wherein step (b) utilizesthe layout layer to program a basic unit for generating the clockedlogic circuit.
 5. The method of claim 1 wherein step (b) utilizes thelayout layer to program a plurality of basic units for generating theclocked logic circuit.
 6. The method of claim 1 wherein step (b)utilizes the layout layer to program a basic unit for generating thenon-clocked logic circuit.
 7. The method of claim 1 wherein step (b)utilizes the layout layer to program a plurality of basic units forgenerating the non-clocked logic circuit.
 8. The method of claim 1wherein step (a) forms at least a PMOS transistor and at least an NMOStransistor within each of the basic units.
 9. A method of fabricating anintegrated circuit, the integrated circuit having a semiconductor body,the method comprising following steps: (a)forming a plurality of basicunits on the semiconductor body, each of the basic units having aplurality of first transistors cascaded in a series and a plurality ofsecond transistors cascaded in a series; and (b)forming at least alayout layer to program traces among the first transistors and thesecond transistors of at least a basic unit for controlling the basicunit to form either a clocked logic circuit or a non-clocked logiccircuit.
 10. The method of claim 9 wherein the first transistors are notelectrically connected to the second transistors before the traces areprogrammed.
 11. The method of claim 9 wherein the first transistors andthe second transistors are MOS transistors.
 12. The method of claim 11wherein the first transistors are PMOS transistors, and the secondtransistors are NMOS transistors.
 13. The method of claim 9 wherein step(b) utilizes the layout layer to program the basic units for generatingthe clocked logic circuit.
 14. The method of claim 9 wherein step (b)utilizes the layout layer to program the basic units for generating thenon-clocked logic circuit.
 15. An integrated circuit comprising: asemiconductor body for positioning a plurality of basic unit, each ofthe basic units having an identical device characteristic; a clockedlogic circuit formed on the semiconductor body, the clocked logiccircuit being formed by at least a basic unit; and a non-clocked logiccircuit formed on the semiconductor body, the non-clocked logic circuitbeing formed by at least a basic unit; wherein the semiconductor bodydoes not limit locations of the clocked logic circuit and thenon-clocked logic circuit on the semiconductor body.
 16. The integratedcircuit of claim 15 wherein each of the basic units comprises at least atransistor.
 17. The integrated circuit of claim 16 wherein thetransistor is a MOS transistor.
 18. The integrated circuit of claim 15wherein each of the basic units comprises at lease a PMOS transistor andat least an NMOS transistor.
 19. An integrated circuit comprising: asemiconductor body for positioning a plurality of basic units, each ofthe basic units having a plurality of first transistors cascaded in aseries and a plurality of second transistors cascaded in a series; aclocked logic circuit formed on the semiconductor body, the clockedlogic circuit being formed by at least a basic unit; and a non-clockedlogic circuit formed on the semiconductor, the non-clocked logic circuitbeing formed by at least a basic unit.
 20. The integrated circuit ofclaim 19 wherein the first transistors are not electrically connected tothe second transistors.
 21. The integrated circuit of claim 19 whereinthe first transistors and the second transistors are MOS transistors.22. The integrated circuit of claim 21 wherein the first transistors arePMOS transistors, and the second transistors are NMOS transistors.